In a typical integrated circuit design process, a circuit schematic of an integrated circuit being designed is generated first, for example, in a schematic editor. A pre-layout simulation is performed on the circuit schematic to simulate the performance of the integrated circuit. Since the layout of the integrated circuit has not been created yet at the time the pre-layout simulation is performed, the layout-dependent effects (LDEs) of the layout of the integrated circuit cannot be taken into the account of the pre-layout simulation. Instead, in the pre-layout simulation, default values of the LDEs are assumed.
Following the pre-layout simulation, the layout of the integrated circuit is generated, for example, using a layout editor. A design verification is then performed on the layout, wherein the design verification includes design rule check (DRC), layout versus schematic verification (LVS), layout parameter extraction (LPE), and parasitic extraction (RCX).
A post-layout simulation is then performed on the layout. In the post-layout simulation, the LDEs are taken into account, so that the generated circuit performance parameters reflect the actual circuit more accurately. The circuit performance parameters are then compared to the design specification. If the circuit performance parameters meet the requirement of the design specification, the design can be signed off. Otherwise, the design process loops back to the schematic generation and editing steps, and the steps including the pre-layout simulation, the layout creation, the design verification, and the post-layout simulation are repeated to modify the design. The loop is repeated until eventually the circuit performance parameters meet the requirement of the design specification.
In the convention design, there is a gap between the pre-layout simulation and the post-layout simulation. Since the pre-layout simulation does not accurately reflect the circuit performance, it becomes costly to realize that the circuit needs to be modified until post-layout simulation, at which time all of the layout of the integrated circuit have been finished.
In advanced nanometer CMOS design, LDEs exert stronger influence than in older generations of circuits on device characteristics, such as current capability for digital circuits, output impedance, and trans-conductance of analog circuits. Therefore, the gap between the pre-layout simulation and the post-layout simulation is severe enough to force designers to reserve extra design margin than before. The achievable speed performance is thus significantly sacrificed.